A Delay Locked Loop (DLL) operates to compare a periodic input signal, such as a clock input, with a clock output signal, and sets a delay line between the input and output signals in a way that the phase differences between these two signals becomes zero.
U.S. Pat. No. 4,795,985 (Gailbreath, Jr.), issued on Jan. 3, 1989, discloses a digital phase locked loop comprising a crystal oscillator, a programmable delay line, a phase detector, and a loop control state machine. The crystal oscillator generates a reference clock signal at a predetermined frequency and provides it as an input to the programmable delay line. The delay line provides up to X nanoseconds of delay corresponding to one complete period of the reference clock in discrete steps of Y nanoseconds. The output of the delay line is compared to digitized data transitions in the phase detector, and if the reference clock leads or lags the data transitions, the state machine provides control signals to program the delay line in a direction that minimizes the phase error between the data transitions and the reference clock signal output by the delay line.
Referring now to FIG. 1, there is shown two possible versions of an exemplary prior art Delay Locked Loop (DLL) arrangement 10 (shown within a dashed line rectangle) for synchronizing an input clock signal to an output clock signal. A first version of the DLL arrangement 10 comprises a first receiver 20, a programmable delay line 22, a driver 24, a first optional feedback path 25 (shown by a dashed line) with a delay element 26 (shown as a dashed line block) providing a delay of [R+D] coupled therein, and a phase comparator 28. The first receiver 20 receives the input clock signal and generates a corresponding clock output signal with an inherent delay of [R] introduced by the internal circuitry of the first receiver 20. The output signal from the first receiver 20 is provided as an input to the delay line 22 and to a first input of the phase comparator 28. The delay line 22 is programmable and introduces a selective delay into the clock signal from the first receiver 20 dependent on a control signal from the phase comparator 28. The delay line 22 provides a clock output signal with a delay of [T-D], where T is the period, or a multiple of the period, of the output clock signal from the DLL arrangement 10, and D is the anticipated delay to be introduced by the circuitry of the driver 24. The Driver 24 receives the output signal from the delay line 22 and, after introducing its inherent internal delay [D], provides a clock output signal from the DLL arrangement 10 which has a delay of [T] which corresponds to a multiple of the period of the output clock when correct compensation is provided by the DLL arrangement 10. When the output clock signal has the delay [T], then it is in phase with the input clock signal. The first optional feedback path 25 couples the output from the delay line 22 to an input of the delay element 26 which provides a delay of R+D to generate an output signal with a delay of T+R that is provided to a second input of the phase comparator 28. The phase comparator 28 compares the phase of the output signals from the first receiver 20 and the delay element 26, and generates an output control signal corresponding to the results of the comparison to the delay line 22. The control signal from the phase comparator 28 causes the delay line 22 to selectively make adjustments to the delay therein as indicated by the control signal. A disadvantage of the first version of the arrangement 10 is that the loading of the driver 24 and its associated delay cannot be taken into account for different loading conditions. For example, the number of Dual Inline memory Modules (DIMMs) on a board can vary considerably to provide different loading conditions on the driver 24.
Theoretically, this disadvantage can be overcome by a second version of the DLL arrangement 10. In this second version, the first receiver 20, the programmable delay line 22, the driver 24, and the phase comparator 28 of the first version remain, but a second optional feedback path 30 (shown by a dashed line) replaces the feedback path 25 of the first version of the DLL arrangement 10. The second optional feedback path 30 feeds back the clock signal present at the output of the driver 24 via a second receiver 32 (shown by a dashed line block) to the second input of the phase comparator 28. The second receiver 32 effectively has the same internal delay [R] as the first receiver 20.
Referring now to FIG. 2, there is shown typical voltage waveforms for a clock signal 35 and a DDR data (DQ) signal 36 versus time. A DLL arrangement 10 produces a negative delay clock output according to the principle described above to get the result shown by the clock signal 35. The DQ signal 36 is represented in FIG. 2 by both positive and negative DDR pulses during each high and low clock pulse because it is not known whether the DDR data is high or low during each high and low clock pulse. Therefore, for a Double Data Rate (DDR) transmission, one bit of DDR data is generated during the high clock pulse and one bit of DDR data is generated during the low clock pulse of the clock period 37. Since DQ data (not shown in FIG. 1) arrives at an output of the DDL 10 in a random way, the output signal of the second version of the DDL arrangement 10 (with the second optional feedback path 30) cannot be used. Instead, an arrangement according to the principles of the first version of the DDL arrangement 10 (with the first optional feedback path 25) has to be used. The drawback of such method is that the loading of the Driver 24 is not taken into account. Since the number of Dual Inline Memory Modules (DIMMS) on a board can vary considerably, the resulting load variations on a data (DQ) line can be very important since the prospective DDR timing allows for a CLOCK/DQ skew of only .+-.1 nanosecond at 100 Megahertz. There are many contributors that produce this skew, and the offset introduced by the load variations makes the functionality of the DDR scheme with DLL questionable.
It is desirable to provide an arrangement which permits DDR data to be outputted in synchronization with a predetermined clock signal in DDR SDRAM applications without concern about output loading.